1. Field of the Invention
This invention relates to a nonvolatile memory, more specifically to array structures and operation methods of the same. The xe2x80x9coperation methodsxe2x80x9d means programming (write and/or erase) and read methods.
2. Description of Related Art
In the U.S. patent application specifications No. 60/147,258 filed on Aug. 5, 1999 and No. 60/158,966 filed on Oct. 12, 1999, array structures of nonvolatile memory are described. In the prior patent applications there was described an array of a nonvolatile memory of prior art constructed of a plurality of the cells. A planar view of the nonvolatile memory of prior art is shown in FIG. 1. The array is two dimensionally disposed, in a first direction and in a second direction. A first set of bit lines 41 and a second set of bit lines 42 extend in the second direction and are continuously connected. The regions 41 and 42 of opposite conductivity are shared with neighboring cells in the first direction. A conductive word line 60 extends in the first direction and stitches a row of third conductive gates 63 together, across and over the opposite conductivity type regions. An example of processing technology for stitching the third conductive gates 63 was described in the patent application No. 60/158,966. Control lines are formed from conductive gates 61 and 62 extending in the second direction and are continuously connected.
A cross section view of a portion of FIG. 1 is shown in FIG. 2. A memory cell is shown with a channel forming a semiconductor region 31, 32 and 33 of a first conductivity type in a surface region 20 called a well on or in one surface of a substrate 10. The substrate 10 is a semiconductor substrate, or has a semiconductor surface layer 20 on an insulating substrate. A first opposite conductivity type region 41 and a second opposite conductivity type region 42 are disposed in the surface 20 of the substrate 10. The first and second opposite conductivity type regions 41, 42 are spaced apart and separated from each other by the channel forming semiconductor region 31, 32 and 33. The channel forming semiconductor region 31, 32 and 33 contain a first channel forming region 31 laterally contacting the first opposite conductivity type region 41, a second channel forming region 32 contacting the second opposite conductivity type region 42, and a third channel forming region 33 disposed between and in contact with the first and second channel forming regions 31, 32. A first gate insulator 51 is disposed on the first channel-forming region 31, and a second gate insulator 52 disposed on the second channel-forming region 32. A third gate insulator 53 is disposed on the third channel-forming region 33. A first conductive gate 61 is formed on the first gate insulator 51, a second conductive gate 62 is formed on the second gate insulator 52, and a third conductive gate 63 is formed on the third gate insulator 53. The first, second and third conductive gates 61, 62 and 63 are electrically insulated each other with an insulator 71 and 72. Carrier trapping sites are contained within gate insulators for carrier storage and are provided in the first insulator 51 and second insulator 52.
It can be recognized from FIG. 1 that the high bit density of 3F2/bit is possible when the conductive first and second gates are fabricated by a side wall gate technology as was shown in the patent application No. 60/158,966. However, to utilize this array in a fast read application under low supply voltage (e.g. Vdd=1.8V), read current per cell is set to be 10xcx9c40 micro-ampere. On the other hand, series resistance of the bit line being comprised of the continuously connected opposite conductivity type regions is about 400 ohm/cell and voltage drop per cell in the bit line amounts to 4xcx9c16mV/cell. In case that 20% voltage drop on the bit line is allowed, only 23xcx9c90 cells can be connected through one bit line. For an array structure larger than 128 bit/bit-line, the opposite conductivity type regions silicided on the top and/or a metal layer stitching every tens (hundreds for the silicided opposite conductivity type regions) of cells is necessary. However, once the metal layer is used for array connection, the above estimated high bit density of 3F2/bit becomes difficult, because usually metal layer pitch is (about 1.4 times) larger than that of a poly-silicon layer. Also the technology cited above for stitching the third conductive gates by one of the word lines is not logic compatible (ie. not compatible with a fabrication process for a MOS logic LSI). For a reasonably high density and/or improved logic compatibility, a new array structure is necessary.
Referring to FIG. 3, an equivalent circuit is shown of the array in FIG. 1. As is seen in FIG. 3, control lines 61 and 62 along with bit lines 41 and 42 cross the word lines 60. When a selected memory cell is written, read or erased, the control lines give a bias voltage(s) to the first and second gates of all unselected cells that are connected to the control lines, causing the unselected cells to suffer from repetitive write disturb, read disturb or erase disturb.
It is a purpose of the present invention to provide a nonvolatile memory array structure having low bit line resistance but still reasonable high cell density. It is another purpose of the present invention to provide a nonvolatile memory array having improved logic process compatibility. It is further another purpose of the present invention to provide an operation method of the nonvolatile memory array. The xe2x80x9coperation methodxe2x80x9d includes xe2x80x9cwritexe2x80x9d, xe2x80x9cerasexe2x80x9d or xe2x80x9creadxe2x80x9d methods. It is further another purpose of the present invention to provide an array structure with improved write, read or erase disturb.
To achieve the above purpose, the following array structure is provided in the present invention. A bit line extends in a first direction and comprises of a high conductive layer, such as a metal layer or a TiN or tungsten layer for a local interconnection. The xe2x80x9chigh conductivexe2x80x9d layer is defined as a layer whose conductivity is higher than that of the opposite conductivity type region. A connection region is provided to connect opposite conductivity type regions neighboring in a second direction, each one of which is shared by two neighboring memory cells extending in the first direction. The connection region is connected to the bit line, thus 4 cells are connected to one bit line through the connecting region and a high-density array structure is obtained. The connection region can be continuously formed to the opposite conductivity type regions and/or simultaneously formed with opposite conductivity type regions for the economy of the processing steps. The connection region can also be a polysilicon layer which contacts the opposite conductivity type region and insulated from a first and second conductive gates mentioned below. This new architecture eliminates the necessity of the word line to cross over the opposite conductivity type regions, which is incompatible with a logic process.
More specifically, the present invention is summarized as a nonvolatile memory array comprising; a plurality of memory cells two dimensionally disposed in a first direction and in a second direction having connection regions with conductive bit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines extending in the second direction. The memory cell comprises a channel forming semiconductor region of a first conductivity type in a semiconductor surface region of a substrate where the substrate is a semiconductor substrate itself, or a semiconductor surface region on an insulating substrate, such as silicon on insulator (SOI). The memory cell also comprises a first opposite conductivity type region and a second opposite conductivity type region being disposed in the surface region of the substrate and the first and second opposite conductivity type regions being spaced apart and separated from each other by the channel forming semiconductor region.
The channel forming semiconductor region further comprises a first channel forming region laterally contacting the first opposite conductivity type region, a second channel forming region contacting the second opposite conductivity type region, and a third channel forming region in contact with the first and second channel forming regions and disposed between the first channel forming region and the second channel forming region. The gate insulators comprise a first gate insulator disposed on the first channel forming region and a part of the first opposite conductivity type region adjacent to the first channel forming region, a second gate insulator disposed on the second channel forming region and a part of the second opposite conductivity type region adjacent to the second channel forming region, and a third gate insulator disposed on the third channel forming region. The conductive gates comprise a first conductive gate on the first gate insulator, a second conductive gate on the second gate insulator, and a third conductive gate on the third gate insulator. The first, second and third conductive gates are electrically insulated from each other, and a part of the first conductive gate overlaps a part of the first opposite conductivity type region via the first insulator. A part of the second conductive gate overlaps over a part of the second opposite conductivity type region via the second insulator. Carrier trapping sites for carrier storage are provided in the first and second insulator.
The connection regions comprise a first connection region and a second connection region. The first connection region electrically connects the first opposite conductivity type regions of two neighboring cells in the second direction. The second connection region electrically connects the second opposite conductivity type region of one of the cells and a second opposite conductivity type region of a neighboring cell in the second direction. The first connection region is connected to a first high conductive layer that is insulated from and crosses over the first, second and third conducting gates. The second connection region is connected to a second high conductive layer that is insulated from and crosses over the first, second and third conducting gates. The first and second high conductive layers form bit lines.
The connection regions can be of opposite conductivity type semiconductor regions. More specifically, the connection regions can be formed continuously in opposite conductivity type semiconductor regions of the memory cells that will be connected to the connection regions. The connection regions can be poly-silicon layers partly over but insulated from the first or second conductive gates. The third gate of each cell is disposed side-by-side in the second direction and is continuous, connecting third gates of other cells together and forming a part of one word line out of the plurality of word lines. The first gate of each cell is disposed side-by-side in the second direction and is continuous, connected to other first gates, and forming a part of a first control line out of the plurality of control lines. The second gate of each cell is disposed side-by-side in the second direction, and is continuous, connected other second gates, and forming a part of a second control line out of the plurality of control lines.
A word line is made from poly-silicon by continuously connecting the third gates. Reduction of the word line resistance can be realized by stitching the word line at each tens or hundreds of cells by a metal layer commonly utilized in a multi-layer interconnection technology. To stitch a control line by a metal layer, a xe2x80x9cbridgingxe2x80x9d layer is provided in the present invention. The xe2x80x9cbridgingxe2x80x9d layer bridges neighboring control gates and connects the neighboring control gates in the first direction. The bridging layer can be made from poly-silicon In order to operate the present array architecture, a new operation algorithm is provided, in the present invention, for writing and reading the array, that is called, xe2x80x9csplit writexe2x80x9d and xe2x80x9csplit readxe2x80x9d. The split write employs three bit lines for writing a pair of hard bits in the cells sandwiched by the two bit lines. A center bit line is biased to a voltage for the acceleration-injection of electrons and the bit lines to either side of the center bit line of the three bit lines are biased to a write-inhibit voltage or a write-select voltage. The write-select voltage can be 0V for 2 level storage, but can be selected from of a multiple of voltages, e.g. 0, 0.5, 1, 1.5V, for setting a storage level in a multilevel storage. Each bit-line adjacent to the selected triplet of bit lines is idled by a bias voltage from 0V to the write-inhibit voltage. Thus every other two hard bits are written.
A split read also employs three bit lines for sensing a pair of hard bits in two cells sandwiched between the two outside bit lines of the selected three bit lines. A center bit line is biased to a read selection voltage, can be 0V for 2 level storage, but can be selected out of a multiple voltages for multilevel sensing. The bit lines on the outside of the selected three bit lines are used for sensing by applying a read voltage. The sensing can be done by either detecting current value through the bit lines or discharge time on pre-charged bit lines. Each bit-line adjacent to the selected triplet of bit lines is idle and biased to a read-inhibit voltage. Thus every other two hard bits are sensed.
The detailed explanation of the algorithm through embodiments will be given after the following explanation of embodiment of array architectures according to the present invention.